The present invention relates to power mesh designs for semiconductor devices, and more particularly to a power distribution system for high power consumption, high pin-count chips designed for use in wire-bond and flip-chip packages.
Integrated circuits are typically packaged before they are used as other components as part of a larger electronic system. A ball grid array (BGA) is a popular surface mount chip package that uses a grid of solder balls to connect the package to a printed circuit board. The chips within the package may be wire bond or flip-chips. Wire-bond BGA packages are constructed with die mounted on a substrate with bond pads on the die connected to conductive lines or traces on the surface of the substrate. Flip-chips have solder balls placed on the surface of the chip, and the chip is xe2x80x9cflippedxe2x80x9d over onto the substrate and connected via the solder balls. One area of concern for BGA packages is power distribution to the die.
FIG. 1 is a top view of a conventional power mesh for redistributing external power across a die. A conventional power distribution system typically uses two metal layers to create a power mesh 10 across a die 12 to supply external power and ground (referred to as VDDCORE and VSSCORE, respectively) to rows of cells 16 within the die 12. Power and ground trunks 12 are placed within the top-metal layer of the die 12 and are usually patterned perpendicular to the rows of cells 16 to permit vias 20 to be placed along the length of the cell rows 16 at regular intervals. In order to provide uniform distribution across the die 12, the metal layer below the top layer also includes power and ground trunks 18, which are patterned parallel to the cell rows 16. This second layer of trunks 18 is connected to the top metal layer trunks 14 using vias 22.
Referring now to FIG. 2, the traditional power mesh system of FIG. 1 is shown in a wire bond ASIC implementation. In the wire bond implementation, an even distribution of VDDCORE and VSSCORE bond pads 30 and 32 is required around the periphery of the die 12 for receiving external power and ground, respectively. I/O signal bond pads 34 are also placed along the periphery of the die 12 for connection with I/O signal lines 36.
Although the traditional power mesh system is well automated within design tools and also provides uniform power distribution across die, the conventional power mesh system includes several drawbacks. First, the power mesh 10 requires at least two metal layers to pattern the perpendicular VDDCORE and VSSCORE trunks 14 and 18. Unfortunately, the layer below the top metal layer is a routing resource that could be used for signal routing rather than for power routing, which could result in smaller die 12 sizes.
Second, the interior of the die 12 may experience a voltage drop due to the length of the VDDCORE and VSSCORE trunks 14 and 18. For example, assuming that the external power source is 5 V, then the die 12 may experience a 5Vxe2x88x9210% drop at the center.
Third, requiring uniform placement of VDDCORE and VSSCORE bond pads 30 and 34 is not ideal from an I/O placement perspective because the uniform placement of the power bond pads require that more I/O signal bond pads 34 be placed towards the corners of the die 12. When I/O signals are forced to the corners of the die 12 in order to connect to the signal I/O bond pads 34, a mismatch between bond wire length and package trace lengths is created, which may cause skew on wide I/O signal lines 36.
The traditional power mesh system 10 also has disadvantages when used in flip-chip implementations, as shown in FIG. 3. FIG. 3 is a top view of a power mesh 10xe2x80x2 used in a conventional flip-chip ASIC implementation. FIG. 3 is a more detailed view showing that each trunk on the top metal layer actually includes a separate VDDCORE trunk 14a and VSSCORE trunk 14b, and each trunk on the layer beneath the top layer also includes a VDDCORE trunk 18a and VSSCORE trunk 18b. 
As stated above, the top metal layer in flip-chips is reserved for I/O to flip-chip solder bump connections, which include VDDCORE bumps 40 and VSSCORE bumps 42. However, the traditional power mesh 10xe2x80x2 also uses the top metal layer. Therefore, when the traditional power mesh 10xe2x80x2 is used with a flip-chip, routing on the top metal layer becomes very congested. For core limited designs, use of a two metal layer power mesh 10xe2x80x2 constrains routing.
In addition, the VDDCORE bumps 40 and VSSCORE bumps 42 are not necessarily evenly distributed across the die 12xe2x80x2; they are usually located on the center of the die 12xe2x80x2 and the power mesh 10 must distribute current from the bumps 40 and 42 to the corners of the die 12xe2x80x2. Because via connections 22xe2x80x2 are used to carry current from the center of the die 12xe2x80x2 towards the corners of the die 12xe2x80x2 in a staircase fashion across the orthogonal mesh power mesh 10xe2x80x2, additional resistance and routing blockages may be introduced. Furthermore, potential IR drops may also occur if there are large current sinks 44 at the die corners.
Accordingly, what is needed is an approved single-layer power mesh that achieves symmetry in power distribution both within the die and through the power pads. The present invention addresses such a need.
The present invention provides a system and method for distributing external power across a die, which has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.
According to the method system disclosed herein, because the trunks are routed diagonally across the die, all the power bond pads can be connected without the need for a second layer, thereby providing a single-layer power mesh. The single-layer power mesh of the present invention achieves symmetry in power distribution both within the die and an even distribution of current flow. In addition, the single-layer power mesh frees a routing resource for signal routing.